Trench MOS barrier Schottky (TMBS) diodes, also known as metal-semiconductor diodes, are semiconductor devices that debuted in recent years. The TMBS devices feature a low power consumption, large current and ultra high speed. In a TMBS device, a metal is formed in contact with a semiconductor material so as to form a potential barrier (usually called surface barrier or Schottky barrier) at the interface of the metal and the semiconductor material. This potential barrier enables the TMBS device to function as a rectifier or detector. As minority charge carriers in Schottky diodes have a minimal charge storage effect, the frequency response of such devices is limited merely by their RC time constant. Thus, Schottky diodes are ideal devices for high frequency and high switching speed applications.
FIGS. 1 to 5 are schematic cross sections illustrating steps for forming a gate dielectric layer and gates in a conventional process for fabricating a TMBS device, the steps including:
S1) providing a semiconductor substrate 10 which may be implemented as a silicon substrate;
S2) forming a hard mask layer 20 over the semiconductor substrate 10;
S3) successively etching the hard mask layer 20 and the semiconductor substrate 10 to form a plurality of trenches 11 in the semiconductor substrate 10, as shown in FIG. 1;
S4) forming a gate dielectric layer 30 over sidewalls of the plurality of trenches 11, wherein forming the gate dielectric layer 30 may further include the steps of: forming a sacrificial oxide layer (not shown) over the sidewalls of the trenches 11; removing the sacrificial oxide layer by hydrofluoric acid (HF) dip; and forming the gate dielectric layer 30, as shown in FIG. 2;
S5) forming a gate layer (not shown) in the trenches 11 and over the gate dielectric layer 30 and over the hard mask layer 20 and etching the gate layer to form gates 40, such that the hard mask layer 20 is exposed and the gates 40 are substantially flush with the gate dielectric layer 30 at the top, as shown in FIG. 3;
S6) forming an intermediate dielectric layer 50 over the hard mask layer 20, the gate dielectric layer 30 and the gates 40 and densifying the intermediate dielectric layer 50, as shown in FIG. 4; and
S7) successively etching the intermediate dielectric layer 50 and the hard mask layer 20 to form a window for subsequently forming holes and contacts, wherein the gates 40 and a portion of the semiconductor substrate 10 are exposed in the window, as shown in FIG. 5, in order to facilitate the subsequent formation of the holes and contacts.
In step S7, the intermediate dielectric layer 50 and the hard mask layer 20 are etched by dry etching, i.e., using plasma of an etchant gas. However, conventional plasma etching process takes 180 s when used to etch a surface dielectric layer with a thickness of 10000 Å. As the plasma is distributed not uniformly in a reaction chamber of the used etching apparatus, i.e., having a higher concentration in a central region than in a peripheral region, the dielectric layer is accordingly etched away at a higher speed in a corresponding central area than in a corresponding peripheral area. This results in a thickness difference of about 200 Å every minute between the two areas of the dielectric layer. At such a pace, the 180 seconds' etching will totally introduce a thickness non-uniformity of at least 600 Å to the dielectric layer.
Further, the intermediate dielectric layer 50 is required to be formed to a large thickness that is generally up to 10000 Å. However, due to equipment constraints, for such a large thickness, the intermediate dielectric layer 50 will originally have a certain thickness non-uniformity itself, 800 Å for each 10000 Å, introduced from its formation process. Therefore, after the dry etching process in step S7, the intermediate dielectric layer 50 will have a total thickness non-uniformity of about 1400 Å. This means after the intermediate dielectric layer 50 and the hard mask layer 20 are etched in step S7, there will either be an up to 1400 Å thick residue of the intermediate dielectric layer 50 or a portion of the gate dielectric layer 30 that is over-etched by 1400 Å. In the embodiment shown in FIG. 5, in order to totally remove the target portions of the intermediate dielectric layer 50 and the hard mask layer 20 located in the window for forming holes and contacts, the over-etching scheme is selected, i.e., the etching time is extended. As a result, portions of the gate dielectric layer 30 covering the sidewalls of the trenches 11 is over-etched, as indicated by the dashed oblong in FIG. 5.
When the over-etched thickness of the portions of the gate dielectric layer 30 is larger than 1200 Å, the yield of the TMBS device being fabricated will decrease. On the other hand, the yield of the TMBS device will also be adversely affected when the etched amount is reduced to an insufficient extent which leads to a residue of the dielectric layer.